1. Field of the Invention
The present invention relates to an overvoltage protection circuit for protecting an overvoltage corresponding to a predetermined wide range of input voltage and relates to a power supply apparatus for the overvoltage protection circuit.
2. Description of Related Art
A commercial power supply voltage has been known to be different in each country, and commercial power supply voltages with AC voltages from 100 V to 240 V exist. As a power supply apparatus used for these power source voltages, a power supply apparatus exists, which is called a worldwide specification and corresponds to the commercial power supply voltages with AC voltages from 100 V to 240 V. For example, it has been already known that an AC adapter is compatible with the worldwide specification and a single type thereof can be sold to any country, thus enabling reduction in man-hour and cost for inventory management and development.
However, the power supply apparatus of the worldwide specification has a problem where the commercial power supply voltage, namely the input voltage of the power supply apparatus, varies widely, causing an input capacitor to become large especially in a capacitor input method and making it difficult to design a power supply circuit portion.
For solving this problem, there has been known an overvoltage protection circuit that supplies a desired voltage (for example, DC 140 V) to an input capacitor and a power supply circuit portion by clamping an input voltage even when the input voltage is a high voltage (for example, see Patent Document 1).
The overvoltage protection circuit includes, for example, a rectifier circuit that receives an input of an AC voltage, and outputs a rectified voltage, a load including an input capacitor, and a semiconductor switch connected between the rectifier circuit and the load. In this case, the overvoltage protection circuit turns off the semiconductor switch when the rectified voltage exceeds a desired value, and the overvoltage protection circuit turns on the semiconductor switch in an interval when a voltage potential difference (V) between both ends of the semiconductor switch is zero or a predetermined minute value (the minute value is a value close to zero, for example, −10−2 to +10−2, etc.). In this manner, it is possible to supply a desired voltage to the input capacitor and the power supply circuit portion.
FIG. 1 is a circuit diagram showing a configuration of an overvoltage protection circuit according to a conventional example disclosed in, for example, Non-Patent Document 1. Referring to FIG. 1, the overvoltage protection circuit includes input terminals T1 and T2, a rectifier circuit 102, a control circuit 103, a semiconductor switch 104 made up of, for example, a MOS transistor, and an input capacitor 105. In this case, the overvoltage protection circuit is inserted between an AC power supply 101 and a load 106.
The AC power supply 101 generates an AC voltage, and outputs the AC voltage via the input terminals T1 and T2 and the rectifier circuit 102, to output a full-wave rectified voltage V01 to the load 106. In parallel with the rectifier circuit 102, a series circuit of the semiconductor switch 104 and the input capacitor 105 is connected to the load 106. The control circuit 103 outputs a control voltage V03 to a gate (control terminal) of the semiconductor switch 104 in accordance with the rectified voltage V01 and a drain voltage V02 of the semiconductor switch 104 to control a drain current I01 of the semiconductor switch 104 and controls the switching operation of the semiconductor switch 104.
FIG. 2 is a timing chart showing an operation in the overvoltage protection circuit of FIG. 1 at a timing when the voltage of the AC power supply 101 is lower than a predetermined value and a load voltage V04 does not need to be clamped. Referring to FIG. 2, due to no need for clamping, the control circuit 103 controls the semiconductor switch 104 so as to be always kept in an on-state. Therefore, the voltage V04 is equal to the voltage V01.
FIG. 3 is a timing chart showing an operation in the overvoltage protection circuit of FIG. 1 at a timing when the voltage of the AC power supply 101 is higher than a predetermined value and the load voltage V04 needs to be clamped. Referring to FIG. 3, the control circuit 103 monitors the rectified voltage V01, and turns off the semiconductor switch 104 when the rectified voltage V01 exceeds a predetermined voltage lower than withstand voltages of the input capacitor 105 and the load 106. Therefore, in the case of the high voltage V01 equal to or higher than the predetermined value, the voltage is not applied to the input capacitor 105 or the load 106, and the voltage V04 is controlled so as to be lower than the withstand voltages of the input capacitor 105 and the load 106. Thereafter, the voltage V04 decreases due to the increase in the current of the load 106, and when the voltage V02 becomes zero or becomes sufficiently small, the control circuit 103 turns on the semiconductor switch 104. When the semiconductor switch 104 is turned on with the voltage V01 at a predetermined voltage without following the voltage V02, a large current flows through the semiconductor switch 104 in a state where the drain-source voltage is high, which results in a large loss in the semiconductor switch 104.
In the overvoltage protection circuit configured as described above, even when the AC power supply 101 is a worldwide AC voltage, the withstand voltages of the input capacitor 105 and the load 106 can be lowered to reduce the size of the input capacitor 105. In addition, the parts performance of the load 106 can be improved. Further, due to limitations on the voltage range applied to the load 106, it is possible to facilitate the design of the load 106.
FIG. 4 is a circuit diagram showing the configuration of the control circuit 103 of FIG. 1. Referring to FIG. 4, the control circuit 103 includes voltage dividing resistors 201 and 202, a reference voltage source 203, comparators 204, 205, and a delay type flip-flop (hereinafter, referred to as DFF) 206. The comparator 204 outputs a high-level reset signal to a reset terminal of the DFF 206 when a voltage V21, obtained by the voltage dividing resistors 201 and 202 dividing the rectified voltage V01, exceeds a reference voltage V22 of the reference voltage source 203. The comparator 205 outputs a high-level signal to a clock terminal of the DFF 206 when detecting that the voltage V02 falls below a reference voltage GND. At this time, the DFF 206 outputs the voltage V03. In this case, the DFF 206 outputs a low-level voltage V03 when the voltage V01 exceeds a predetermined voltage, and outputs a high-level voltage V03 after the voltage V02 becomes zero or sufficiently small.
In the conventional example of FIG. 1, it is expected that the steep rise and fall of the current I01 cause deterioration in a conduction disturbing wave voltage. For this reason, a large noise filter is required to pass the regulation on the conduction disturbing wave voltage (for example, CISPR 22 (see Non-Patent Document 2, for example)), and the volume of the power supply apparatus may increase. A steep current fluctuation to the AC power supply 101 causes the conduction disturbing wave voltage, and in order to improve this, it is necessary to suppress the steep current fluctuation to the AC power supply 101.